The present invention relates generally to accessing and controlling memory, and more particularly to memory controllers for multi-rank dynamic random access memory (DRAM) systems.
Memory modules are often designed with two or more independent sets of DRAM chips connected to the same command/address and data buses. Each such set is called a rank. Multiple ranks can coexist on a single dual in-line memory module (DIMM), and modern DIMMs consist of from one to eight ranks per module. Ranks offer a form of memory access parallelism; however, since the ranks on a single DIMM typically share the same command/address and data buses, a DRAM controller can generally access only one rank at a time. In this case, the rank to be accessed is powered up and all other ranks are powered down for the duration of the memory operation. Because such rank switching incurs a delay, DRAM controllers may employ a procedure for rank switching that is designed to increase DRAM bandwidth and improve performance.